Abstract The objective of this study was to evaluate the effect garlic extract on modulation Galectin protein secretion in sheep blood. Dietary supplements can influence innate immunity. Garlic (Allium sativum) and its derivatives are eco-friendly non-antibiotic, growth-promoting dietary known modulate inflammation. Galectins (Gals) a family animal lectins that bind β-galactosides. Secreted Gal...

This paper presents the interface circuit which incorporates the technique of analog value to digital value conversion utilising a self clocking method. The architecture consists of the Globally Asynchronous and Locally Synchronous (GALS) building blocks, where the processing hardware is being realized by the set of smaller slices of similar structure, each running synchronously with independen...

In this paper we consider the problem of desynchronising modular synchronous speci cations for their realisation into GALS architectures and obtaining simple wrappers that are e ciently synthesisable using existing synthesis tools. The systems are modeled using Petri nets (PN) and the desynchronisation technique is based on the theory of PN Localities. The ring semantics of a globally synchrono...

In this paper, we propose an asynchronous wrapper with novel handshake circuits for data communication to be used in GALS systems. The handshake circuits include two communication ports and a local clock controller. We present two approaches for the implementation of communication ports; one with pure standard cells and the other with Müller C elements.The detailed design methodology is given a...

As the number of transistors on a single integrated circuit approach a billion, the problems of clock distribution, power consumption, multiple clock domains, meeting timing requirements, and reuse of subsystem designs grow ever more difficult. Coordinating a billion transistors with the present design methodologies will require hundreds of years of engineering time. A new design methodology is...

The new vision presented is aimed to overcome the logic overhead issues that previous works exhibit when applying GALS techniques to programmable logic devices. The proposed new view relies in a 2-phase, bundled data parity based protocol for data transfer and clock generation tasks. The ability of the introduced methodology for smart real-time delay selection allows the implementation of a var...

Many Processor Systems-on-Chip (MPSoC) have become tremendously complex systems. They are more sensitive to variability with technology scaling, which complicates the system design and impact the overall performance. Energy consumption is also of great interest for mobile platforms powered by battery and power management techniques, mainly based on Dynamic Voltage and Frequency Scaling (DVFS) a...

Networks-on-Chip (NoCs) are a new paradigm for the design of integrated systems. NoCs address design complexity and physical issues in ASIC and FPGA designs. In this paper, we present a scalable, mesochronous NoC architecture for an FPGA. A special hybrid switching scheme has been developed for globally asynchronous locally synchronous (GALS) operation of the whole NoC-based system. The NoC was...

This paper describes an extension to Lustre to support the analysis of globally asynchronous, locally synchronous (GALS) architectures. This extension consists of constructs for directly specifying the timeout automata used to describe asynchronous communication between processes represented by Lustre nodes. It is implemented using an extensible language framework based on attribute grammars th...