We have developed a manufacturing process for organic thin-film transistors and organic complementary circuits in which a microcontact-printed phosphonic acid self-assembled monolayer is employed first as an etch resist to pattern aluminum gate electrodes by wet etching and then as the gate dielectric of the same device. To our knowledge, this is the first report of a printing process for elect...

DC and intrinsic low-frequency noise properties of p-channel depletion-mode carbon nanotube field effect transistors (CNT-FETs) are investigated. To characterize the intrinsic noise properties, a thin atomic layer deposited (ALD) HfO(2) gate dielectric is used as a passivation layer to isolate CNT-FETs from environmental factors. The ALD HfO(2) gate dielectric in these high-performance top-gate...

The present understanding of wear-out and breakdown in ultrathin ( 5 0 nm) SiO2 gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of de...

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. We find that this mem...

Abstract—The origin of negative flat-band shift using La2O3 incorporation in HfO2 dielectrics has been extensively examined. From careful extraction of effective work function of gate electrode and fixed charges at each interface, it has been revealed that La2O3 at high-k/Si substrate or high-k/SiO2 interface has either large amount of positive fixed charges or an additional dipole of 0.36 V co...

In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluatio...

Analytical electron microscopy techniques are used to investigate elemental distributions across a high-k dielectric stack with a metal gate. Electron energy-loss spectroscopy results from a Si(100)/SiO2/HfO2/TiN/a-Si gate stack confirm the presence of an oxide interfacial phase at the TiN/a-Si interface prior to activation of the stack.

The degradation of 100 nm effective channel length pMOS transistors with 14 A equivalent oxide thickness JVD Si3N4 gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concem. Hot-carrier reliability of 14 A Si3N4 transistors is compared to reliability of...

Introduction MOSFETs with a high-mobility channel are attractive candidates for advanced CMOS device structures, since it is becoming increasingly difficult to enhance Si CMOS performance through traditional device scaling. The lower effective mass and higher mobility of carriers in germanium (Ge) compared with silicon (Si) (2x higher mobility for electrons and 4x for holes) has prompted renewe...

Oxygen-related point defects can provide fixed charge or act as charge trapping centers in high-k gate stacks and, therefore, their origins and properties are of great interest. In this paper, reported experimental and theoretical results related to oxygen defects in HfO2 gate dielectrics are reviewed critically to assess the relative importance of different defect species in terms of their ele...