A temperature prediction method of Insulated Gate Bipolar Transistor (IGBT) module based on autoregressive moving average model is proposed. Historical and current temperature datum of IGBT module is indispensable to the ARMA method, temperature time series is obtained by uniform sampling, and autoregressive (AR) model is constructed. Temperature time series prediction of IGBT module is realize...

A novel recognition method for selective determination of the hyoscine N-Butyl bromide (HBB), an antispasmodic agent for smooth muscles, was devised using extended gate field-effect transistor (EG-FET) as transducing unit. For this purpose a PVC membrane, containing hyoscine n-butyl-tetraphenyl borate ion-pair as recognition component, was coated on Ag/AgCl wire, which was connected to the exte...

 A 3-transistor nonvolatile analog storage cell with 14 bits effective resolution and railto-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hotelectron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under fee...

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuitdelay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intrag...

Exclusive NOR (XNOR) gates are very important in electronics department. This is widely used in digital circuits. This paper proposes the novel design of 2T XNOR gate using pass transistor logic. The proposed circuit has the minimum transistor count and there is no complementary input signal is used. This design has been compared and analyzed with earlier designed XNOR gates and a significant i...

Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken deal with for field effect transistor further scale down as semiconductor technology enters into sub-10 nm node. From 3 node beyond, gate all around steps onto the history stage attributed its improved SCE suppressing ability thanks surrounding s...

PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using a state-of-the-art long term prediction model. Experimental evaluations show that the stress probability should be estimated at transistor level to accurately predict the increase in delay, esp...

With the miniaturization of transistor size, fabrication of transistor with lithography technique is a foreseen problem. It is possible to routinely create semiconductor nanocrystals whose dimensions are much smaller than those can be realized by lithography techniques using colloidal chemistry. The size of the nanocrystals can be varied easily by varying the process parameters to study the qua...

S The electrostatics of nanowire transistors are studied by solving the Poisson equation self-consistently with the equilibrium carrier statistics of the nanowire. For a one-dimensional, intrinsic nanowire channel, charge transfer from the metal contacts is important. We examine how the charge transfer depends on the insulator and the metal/semiconductor Schottky barrier height. We also show th...