A compact quadruplexer with the functions of frequency division, selection, and power splitting/combining is presented in this article. Four tri-mode stub-loaded resonators were adopted to construct multifunctional a third-order filtering response. The four-channel passbands controlled realized independently by using distribution coupling configuration. output structure was designed be symmetri...

A log-domain current-mode true RMS-to-DC converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. The circuit employs floating gate MOS (FG-MOS) transistors operating in weak inversion region. The converter features low power(

Superharmonic injection locking is investigated in a new theoretical approach. Low power frequency dividers are designed using injection locked oscillators with cascode transistors. The Rockwell 0:5 m CMOS process is used to design a 3mW injection locked frequency divider in the 1800MHz frequency range. A 200MHz maximum locking range is achieved in simulations. 2SC3302 TOSHIBA NPN transistors a...

A simple and analytical design methodology for a novel planar four-port structure to implement power divider (PD) or balun with variable power division is proposed in this paper. It consists of two different 3 dB branch-line couplers and one coupled-line phase shifter whose length can be changed to implement variable power division. Different from the previous designs, the power divider and bal...

The CMOS PLL based Frequency Synthesizer is a vital role in Receiver front end Sub component. The main objective of this paper is to design a high frequency of oscillation, less phase noise and power efficient PLL. In general, the PLL contains PFD, Loop Filter, VCO and Frequency Divider. The VCO is a critical component in Phase Locked Loop for low power CMOS designs. Here the Source Coupled VCO...

We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling ...