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High-level synthesis (HLS) aims at constructing the optimal hardware or software structure from a given high-level speci cation. This process involves a number of optimization steps, from which scheduling is the most crucial one, concerning both the running time of the process and the quality of the found solution. In this paper, we present a genetic algorithm for the scheduling problem in HLS....

A procedure is defined to be strict if every variable is defined before it is used along every path of program execution. A regular program is a strict procedure in Static Single Assignment (SSA) Form. Recently, it has been proven that the interference graph for regular program is a chordal graph. This yielded an optimal polynomial-time algorithm for register allocation for high-level synthesis...

In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous bu er insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those ...

The effectiveness of traditional compiler techniques employed in high-level synthesis of synchronous circuits aiming to present a generic code is studied for asynchronous synthesis by considering the special features of these circuits. The compiler methods can be used innovatively to improve the synthesis results in both power consumption and area. The compiler methods like speculation, loop in...

We propose a synthesis for test approach in which multiplexers are embedded in the behavioral models of the various modules constituting a hierarchical system. This approach can also be applied to system-on-a-chip designs in which synthesizable models are available for the embedded cores. The embedded multiplexers provide complete, single-cycle transparency, thereby offering a straightforward y...

Power-gating is the most promising run-time technique in order to reduce leakage currents in sub-100nm CMOS devices but its application is associated with numerous problems. Overhead costs in terms of additional state transition costs occur, the targeted circuit is slowed down while being in the active state, additional interfacing circuits are necessary, and in general the total impact of the ...

| Functional debugging of application speci c integrated circuits (ASICs) has been recognized as a very labor-intensive and expensive process. We propose a new approach based on the divide and conquer optimization paradigm for the functional test pattern execution. The goal is to maximize the simultaneous controllability of an arbitrary set of the user selected variables in the design at the de...

This paper presents a formal approach to address the correctness of transformations in high-level synthesis. The novelty of the work is that a small set of properties that capture a general notion of reenement of control/data-ow graphs used in an industrial synthesis framework have been given, and the properties are independent of the underlying behavior model. We have mechanized the speciicati...

One of the primary advantages of a high-level synthesis system is its ability to explore the design space. This paper presents several methodologies for design space exploration that compute all optimal tradeoo points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes advantage of both the structure within the design s...