This paper proposes an approach to reduce the short circuit current of CMOS off-chip drivers by individually controlling the input slew rates to the P and N channel transistors that drive the output pad. The slew rates are deliberately designed such that the N(P) transistor at the output stage will be turned off faster than the P(N) transistor is turned on for low-to-high (highto-low) output tr...

A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE simulations and a 0.25pm CMOS technology with a supply voltage of 2.5V. The impacts of the new technique on dynamic and leakage powers and area are also presented. Q . an...

In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes less power i n a commercial 90n...

In this paper, a reconfigurable, low power four quadrant memristor and carbon nanotube field effect Transistor (CNFET) based analog multiplier is proposed. The circuit is verified by extensive HSPICE simulations using experimentally verified memristor and Stanford CNFET models that have been calibrated for 90% accuracy at the 32nm technology node. The proposed multiplier has an input range of ±...

Sigma-Delta Analog to Digital Converter with digital implementation techniques is simulated. The differential pin based and inverter based architectures are discussed. Simulation of the proposed architecture with Virtex-4 FPGA I/Os is performed and analysis carried out using HSPICE to estimate the typical achievable clock speeds. The results demonstrate 200MHz clock speeds on LVPECL differentia...

Two-phase micro-pipeline asynchronous modules show faster performance than common four-phase control systems, but the conventional systems with multi-port modules normally suffer from long signal paths on stacked C-elements. NOR-based control schemes provide an alternative solution to problems such as propagation delay. This paper compares modified versions of these two popular pipelined system...

Random jitter (RJ) is a significant noise component in PLL systems that use ring-based oscillators. In order to estimate RJ, accurate modeling of the VCO phase noise is essential. In this paper, the authors will present how the VCO phase noise they obtained from HSPICE RF and from the Impulse-Sensitivity Function (ISF) method compared to lab measurements, the limitations of the two methods and ...

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achie...

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET tech...

This paper addresses the impacts of signal slew time and signal skew variations on delay uncertainty and cross talk noise in coupled inductive lines for different switching patterns. Our findings reveal that delay variation in a victim line always increases with the reduction of signal slew time and increase in signal skew. We also observe that cross talk noise reduces with increasing signal sk...