Distributed algorithm is suitable for FPGA to do multiply-accumulate operations, which use the abundant memory resources of FPGA to do look-up table operation. We present a method for implementing high speed Finite Impulse Response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common sub expression elimination algorithm to reduce the number of ad...

Finite-impulse response (FIR) Filter is widely used in wireless sensor networks as a signal pre-processing step. Because sensor nodes require a long working periods and ultra-low cost, traditional FIR structures are inapplicable as multipliers occupy too much die size for such node’s chips. This paper proposes novel FIR filter structures used in the design of application specific integrated cir...

The hardware description and implementation of adaptive infinite-impulse-response (IIR) filters for real-time applications is an important and challenging designing issue. The aim of this paper is hardware description of digital adaptive IIR filters for implementing on field programmable gate array (FPGA) chips. The direct architecture is considered for IIR filter designing and Equation-Error (...

Multiplicative general parameter (MGP) approach to finite impulse response (FIR) filtering introduces a novel way to realize cost effective adaptive filters in compact very large scale integrated circuit (VLSI) implementations used for example in mobile devices. MGP-filter structure comprises of additions and only a small number of multiplications, thus making the structure very simple. Only a ...

This paper presents a novel approach of designing linear phase FIR low pass filter using cuckoo Search Algorithm (CSA). FIR filter design is a multi-modal optimization problem. The conventional optimization techniques are not efficient for digital filter design. An iterative method is introduced to find the best solution of FIR filter design problem.Flat passband and high stopband attenuation a...

The paper presents a simple implementation model of the high-voltage power line communication (HV PLC) channel using digital filters. The model utilizes three identical finite impulse response (FIR) filters. The amplitude characteristic of the FIR filters matches the HV PLC channel amplitude characteristic for a given coupling, without taking into consideration reflection. The reflection phenom...

An improved Infinite Impulse Response (IIR) Least Mean Squares (LMS) algorithm using parallel filters and evolutionary programming techniques is introduced. IIR filters have the attractive property that they require fewer computations than a corresponding FIR filter, but they are prone to instability and local minimum problems. Evolutionary algorithms are good in global optimization scenarios, ...

In DSP based IQ modulators generating CPFSK signals, departures from a flat-magnitude, linear phase frequency response in the pass bands of analogue reconstruction filters in the I and Q channels cause ripples in the modulator output signal envelope. These ripples then produce undesirable side-lobes in the output signal spectrum when the signal passes through non-linear elements in the transmis...

Conventional hardware implementation techniques for FIR filters require the computation of filter coefficients in software and have them stored in memory. This approach is static in the sense that any further fine tuning of the filter requires computation of new coefficients in software. In this paper, we propose an alternate technique for implementing FIR filters in hardware. We store a consid...

– Equalization in the time domain is a wellknown technique for combating intersymbol interference (ISI) in frequency selective channels. In this paper we derive the general structure of the linear zero forcing (ZF) equalizing filters for multiple input multiple output (MIMO) communication systems with more outputs than inputs. These filters are finite impulse response (FIR) filters in general a...