of the Dissertation Scalable Hardware Mechanisms for Superscalar Processors by Steven Daniel Wallace Doctor of Philosophy in Electrical and Computer Engineering University of California, Irvine, 1997 Professor Nader Bagherzadeh, Chair Superscalar processors fetch and execute multiple instructions per cycle. As more instructions can be executed per cycle, an accurate and high bandwidth instructi...

High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to use an optimizing compiler to minimize cache interference via an improved layout of the code. This technique, however , has been applied to application code only, even though there is evidence that the operating system often uses the cache heavily and with less uniform patte...

High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to use an optimizing compiler to minimize cache interference via an improved layout of the code. This technique, however, has been applied to application code only, even though there is evidence that the operating system often uses the cache heavily and with less uniform patter...

Fast Instruction Cache Performance Evaluation DAVID B. WHALLEY Department of Computer Science B-173, Florida State University, Tallahassee, FL 32306, U.S.A. SUMMARY Cache performance has become a very crucial factor in the overall system performance of machines. Effective analysis of a cache design requires the evaluation of the performance of the cache for typical programs that are to be execu...

The instruction footprint of OS-intensive workloads such as web servers, database servers, and file servers typically exceeds the size of the instruction cache (32 KB). Consequently, such workloads incur a lot of i-cache misses, which reduces their performance drastically. Several papers [6, 8, 5, 2, 3] have proposed to improve the performance of such workloads using core specialization. In thi...

Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contributor to these uncertain latencies is the use of cache memories required to provide adequate memory access speed in modern processors. Scheduling for instruction-level parallel architectures with nonblocking caches usua...

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The main contributions of this paper are twofold. First, a general framework for control-ow partitioning is presented for eecient on-they analysis, i.e. for program behavior analysis during execution using a small number of instrumentation points. The formal model is further reened for certain analyses by transforming a program's call graph into a function-instance graph. Performance evaluation...

An Efficient Simulation of application specific instruction-set processors (ASIP) is a challenging onus in the area of VLSI design. This paper reconnoiters the possibility of use of ASIP simulators for ASIP Simulation. This proposed study allow as the simulation of the cache memory design with various ASIP simulators like Simple scalar and VEX. In this paper we have implemented the memory confi...