We compared the high-end Intel Xeon processor X5570 (2.93 GHz) with the low-end Intel® Xeon® processor E5504 (2.0 GHz) for two Intel IT computing environments: design and enterprise. In real-world application testing with Intel’s electronic design automation (EDA) workloads, two-socket servers based on the 2.93GHz processor delivered the same performance for an estimated 42 percent lower TCO ov...

Although the architecture is straightforward and remarkably well-supported, the workings of these components may not be obvious to engineers, programmers, or product developers with no previous Intel architecture experience. This paper describes the basic operations and functions of the relevant components, using three example systems. Specifically, the paper will focus on the Intel® CoreTM i7 ...

Demand for mobile video applications is growing today in wireless handheld platforms. The Intel® PXA27x processor family has been designed to accelerate mobile multimedia and applications processing in a power efficient manner. The PXA27x processor is a highly integrated system on a chip including the Intel XScale® Microarchitecture with 64-bit Intel® Wireless MMXTM technology, 256KBytes of on-...

Adoption of service orientation in all aspects of enterprise computing has gained momentum in recent years. This paper describes research on Service-Oriented Infrastructure (SOI) and key concepts that enable higherlevel service orientation and autonomic computing. We demonstrate how the concept of platform as a service (PaaS) may be applied to a real Information Technology (IT) operational envi...

This paper proposes a DiffServ-over-MPLS Traffic Engineering (TE) architecture and describes the implementation of its functional blocks on Intel IXP2400 Network Processor using Intel IXA SDK 4.1 framework. We propose fast and scalable 6-tuple range-match classifier, which allows traffic policing procedures to operate on per-flow level, and a scalable low-jitter Deficit Round Robin (DRR) schedu...

For the majority of common workloads, performance in a virtualized environment is close to that in a native environment. Virtualization does create some overheads, however. These come from the virtualization of the CPU, the MMU (Memory Management Unit), and the I/O devices. In some of their recent x86 processors AMD and Intel have begun to provide hardware extensions to help bridge this perform...

The innovative Intel® HyperFlexTM FPGA Architecture features a “registers everywhere” design that includes ubiquitous retiming and pipelining registers, called Hyper-Registers. These Hyper-Registers are available in every routing wire on the device. Combined with the new Intel Quartus® Prime Hyper-Aware design flow, these Hyper-Registers allow designers to break the performance barrier, achievi...

In the present paper, an implementation of a parallel one-dimensional fast Fourier transform (FFT) using Streaming SIMD Extensions 3 (SSE3) instructions on dual-core processors is proposed. Combination of vectorization and the block six-step FFT algorithm is shown to effectively improve performance. The performance results for one-dimensional FFTs on dual-core Intel Xeon processors are reported...

In this paper we take a look at what the new Intel instruction extensions Intel Advance Vector Extensions (AVX) brings to high performance computing. We compare two configurations of Intel CPU based systems (one enabled with AVX and a second without AVX enabled) and present a performance evolution of these two platforms. We compare the same generation of CPU utilizing a single socket platform a...

Xen* is an open source virtual machine monitor (VMM) developed at the University of Cambridge to support operating systems (OSs) that have been modified to run on top of the monitor. Intel has extended the Xen VMM to use Intel ® Virtualization Technology ∆ (VT) to support unmodified guest OSs also. This was done for IA-32 Intel ® Architecture processors as well as Itanium ® architecture process...