A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed registe...

To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS i...

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices, result in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Curre...

A high speed and low power CMOS inverter is designed & simulated in this paper. The critical path consists of PMOS and NMOS. The designed inverter cell offers high speed and low power consumption than the CMOS inverter. A Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technique is used to reduce the leakage current as well as leakage power to achieve better results. MTCMOS is ...

Distribution systems across most parts of the globe are highly radial in nature. As loads are gradually increased on a particular distribution system, a higher operating current state leading to increased fault current levels is attained. Hence, the relay co-ordination is disturbed and equipments such as feeders and circuit breakers need to be replaced with higher rating so that they can handle...

We propose a novel IDDQ outlier screening flow through a two-phase approach: a clustering-based filtering and an estimation-based current-threshold determination. In the proposed flow, a clustering technique first filters out chips that have high IDDQ current. Then, in the current-threshold determination phase, device-parameters of the unfiltered chips are estimated based on measured IDDQ curre...

This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fanout effect. The proposed approach uses a new precise macro-modeling of leakage current considering subthreshold leakage, gate tunneling leakage, body effect, stack effect, and fanout effect. The macro-model is developed...

The Internet of Things (IoT) has become more prevalent in recent years and is an integral part everyday life. Thus, the need for ultralow-power sensors processing units dramatically increased. continuous scaling CMOS transistors resulted severe subthreshold leakage high power density issues. In years, microelectromechanical (MEM) relays have attracted research interests. They are viewed as prom...

In this channel,we study rate region of a Gaussian two-way diamond channel which operates in half-duplex mode. In this channel, two transceiver (TR) nodes exchange their messages with the help of two relay nodes. We consider a special case of the Gaussian two-way diamond channels which is called Compute-and-Forward Multiple Access Channel (CF-MAC). In the CF-MAC, the TR nodes transmit their mes...