The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose several design rules for designing the Wall...

the purpose of this study was to investigate the effect of caffeine ingestion on anaerobic power; fatigue index and blood lactate levels in boys athlete students. among voluntarers 16 subjects were selected and devided into two caffeine and placebo groups in a simple – randomized manner base on fatigue index in the pretest. they were asked to prevent from doing intensified activities 24 hours p...

Power quality monitoring has advanced to an important tool for system evaluation and solving power-related problems. As a consequence the increased amount of recorded data requires more sophisticated analysis methods. The paper proposes a system for automated recording and classification of power quality disturbances. The system features statistical classification techniques applied to a frame-...

a new output structure for class e power amplifier (pa) is proposed in this paper. a series lc resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. this resonator causes low impedance at the second harmonic. the output circuit is designed to shape the switch voltage of the class e amplifier and lower the voltage stress of the transistor. t...

background: the people residing in coastal areas of visakhapatnam are mostly engaged in fishery, which is always been a physically demanding job, and numerous factors have direct or indirect impact on the health of fishermen; but, the data about their physical fitness or health status is quite scanty. thus, the present study was conducted to assess their cardiorespiratory fitness pattern, as we...

Test power is major issue of current scenario of VLSI testing. There are different test pattern generation techniques for testing of combinational circuits. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing.