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This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low vo...

This paper presents a negative type secondgeneration current conveyor (CCII-). It is based on an inverter-based low-voltage error amplifier, and a negative current mirror. The CCIIcould be operated in a very low supply voltage such as ±0.5 V. The proposed CCIIhas wide input voltage range (±0.24 V), wide output voltage (±0.24 V) and wide output current range (±24 mA). The proposed CCIIhas no on-...

We present four circuits implemented in subthreshold CMOS which greatly increase the linear range over the basic di erential pair. These circuits are appropriate for low voltage applications since there is no stacking of saturated transistors. The rst circuit topology employs multiple asymmetric di erential pairs. The second is a symmetric \bump" transconductor. The remaining two use source deg...

Low-loss microwave microelectromechanical systems (MEMS) shunt switches are reported that utilize highly compliant serpentine spring folded suspensions together with large area capacitive actuators to achieve low actuation voltages while maintaining sufficient off-state isolation. The RF MEMS switches were fabricated via a surface micromachining process using PI2545 Polyimide 1 as the sacrifici...

In order to cope with the increasing leakage power and the increasing device variability in VLSI’s, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-str...

This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design ...

Query Representation Query Planning &

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. ...