In this paper we present a new test set embedding method for test-per-clock BIST schemes. The method works efficiently with fully specified as well as partially specified test sets and requires a number of clock cycles equal to the size of the test set. The resulting test pattern generation mechanism (TPG) compares favourably in terms of area implementation and test application time to already ...

This paper presents a method for deriving a BIST specification from the initial specification of datapaths. This method minimizes BIST area overhead under test time constraint while guaranteeing a user chosen fault coverage. The designer can thus explore a wide range of solutions and keep the one that best fits with design constraints. Results show great improvements over lower level techniques.

This paper presents a new feedback shift registerbased method for embedding deterministic test patterns on-chip suitable for complementing conventional BIST techniques for infield testing. Our experimental results on 8 real designs show that the presented approach outperforms the bit-flipping approach by 24.7% on average. We also show that it is possible to exploit the uneven distribution of do...

The focus of this work is on how field programmable devices handle faults. More specifically, how physical constraints may hamper fault tolerance techniques. This paper analyzes representative work in exhaustive BIST, voting, FPTA fault tolerance, competitive runtime reconfiguration, and embryonics. Its aim is to examine how the presented techniques perform with added constraints such as space/...

A new technique for diagnosis in a scan-based BIST environment is presented. It allows non-adaptive identification of both the scan cells that capture errors (space information) as well as a subset of the failing test vectors (time information). Having both space and time information allows a faster and more precise diagnosis. Previous techniques for identifying the failing test vectors during ...

With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some...

In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously propo...

In this paper, we propose a new transparent Built-In Self-Diagnosis ( BISD ) method to diagnose multiple embedded memory arrays with various sizes an parallel. A new tmnspamnt diagnostic interface has been proposed to perform testing in n m l mode. By tolerating redundant read/urite/shift operations, we develop a new mamh algorithm called TDiagRSMarch to achieve the y w l s of low hardware over...

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability technique such that high-speed ICs can be tested using inexpensive, lowspeed ATE. Also extensions for possible full BIST of delay faults are ...

At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques is not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique...