This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier, energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multipli...

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two’s complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32...

In this paper, a new architecture for MOS Current Mode Logic (MCML) array multiplier for mixed-signal applications is proposed. The proposed architecture employs active shunt-peaking technique in conventional MCML circuits. The technique of active shunt-peaking offers a way for increasing the speed of MCML gates. The performance of the proposed MCML array multiplier is compared with the convent...

The natural fault-tolerant properties and regular structure of the Lee-Lu-Lee’s array multiplier over GF(2) fields make it very attractive for VLSI implementation. However, the Lee-Lu-Lee’s array multiplier is time-consuming while comparing with other existing array multipliers. Thus, we will present fast array multipliers with multiple speeds as comparing with the Lee-Lu-Lee’s array multiplier.

The subgroup of the Schur multiplier of a finite group G consisting of all cohomology classes whose restriction to any abelian subgroup of G is zero is called the Bogomolov multiplier of G. We prove that if G is quasisimple or almost simple, its Bogomolov multiplier is trivial except for the case of certain covers of PSL(3, 4).

A design of high performance 64 bit Multiplier-andAccumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with Synthesize and simulate by verilog-HDL.

We examine the use of efficient shift-and-add multiplier structures and multiplier blocks to reduce computational complexity in filter banks. This is more efficient than treating each bank filter separately. We also examine the Farrow structure, which is used in interpolators. Applying multiplier blocks makes this structure cheaper than the more recognized Lagrange interpolator.

A multiplier on a normal subsemigroup of a group can be extended to a multiplier on the group. This is used to show that normal cancellative semigroups have the same second cohomology as the group they generate, generalising earlier results of Arveson, ChernofF, and Dinh. The main tool is a dilation theorem for isometric multiplier representations of semigroups.

A new GF(2) redundant representation is presented. Squaring in the representation is almost cost-free. Based on the representation, two multipliers are proposed. The XOR gate complexity of the first multiplier is lower than a recently proposed normal basis multiplier when CN (the complexity of the basis) is larger than 3n-1. Index Terms Finite field, normal basis, redundant set, Massey-Omura mu...

High speed Finite Impulse Response filter (FIR) is designed using the concept of faithfully rounded truncated multiplier and parallel prefix adder. The bit width is also optimized without sacrificing the signal precision. A transposed form of FIR filter is implemented using an improved version of truncated multiplier and parallel prefix adder. Multiplication and addition is frequently required ...