Network-on-a-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance system-on-chip architectures in the nanoscale regime. Many real-time applications require input data that arrives with low delay jitter. Such communication traffic can only be supported by incorporating multiple levels of service in the interconnection network. Further, as tec...

Systems-on-Chip architecture integrates several heterogeneous components on a single chip. A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead. Network-on-chip (NoC) is a new approach for communication infrastructure of Systems-on-Chip (SoC) design, which provides network based solution for on-chip communication....

Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC network-based subsystem on an integrated circuit, most typically modules system (SoC). Designing reliable against failures that can prevent failure using some measures or preventing error while happens and proper performance became significant concern. For design failures...

A low-power packet-switched Network-on-Chip (NoC) is designed with hierarchical star topology and implemented in real silicon for possible application to high-performance SoCs. This dissertation presents how to obtain low power consumption in NoC while the whole NoC design process is covered from the architecture decision to the system demonstration. First, a performance and cost oriented topol...

In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. The portion of transistors devoted to compute operations can be maximized by off-loading as much as possible data-storage onto memory chips. This, however, requires wide off-chip IO bandwidth, and furthermore increases Network-on-chip (NoC) traffic. In this paper, we...

Looking into the future, when the billion transitor ASICs will become reality, this paper presents Network on a chip (NOC) concept and its associated methodology as solution to the design productivity problem. NOC is a network of computational, storage and I/O resources, interconnected by a network of switches. Resources communcate with each other using addressed data packets routed to their de...

Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance evaluation of On-Chip Interconnect (OCI) architectures is widely based on simulation which becomes computationally expensive, especially for largescale NoCs. In this paper, we study

The scale down of transistor technology allows microelectronics manufacturers to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are quickly becoming obsolete as they struggle to sustain the tight bandwidth and latency constraints that the modern embedded systems de...

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. IT is used as a new approach to designing complex System-on-a-chip (SoCs) design. NoC-based systems can accommodate multiple complex SoC designs. In a NoC-based system, modules such as processor cores, memories and specialized IP blocks exchange data using a on-chip n...

Network-on-chip(NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of onand off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essent...