This article proposes a positively coupled inductor (PCI) based paralleling scheme for basic semibridge switching cells, which are formed by power MOSFETs and diodes. Both the cells inductors split into two parallel parts, thus, small differential mode (DM) inductance is between midpoints of cells. A time-delay-based modulation strategy applied to generate controllable circulating current, enab...

Both Benes and Clos networks are rearrangeably non-blocking multi-stage interconnection networks. Benes network is a special case of Clos network which has inputs and outputs. The Benes network is constructed with switching nodes recursively. Due to their non-blocking property and relative smaller number of crosspoints, Benes/Clos networks have received much attention in both academia and indus...

We study the combinatorial problem of switching lattice synthesis. The idea of using regular arrays of switches, each cell connected to its neighbours, is old and has many forms. For example, in the “rectangular logic arrays” of Akers [1972], each switch is a relatively complex 3-input 2-output unit implementing either the median-of-3 function or the Boolean if-then-else function, and switches ...

Research on Reconfigurable Battery Systems (RBS) is gaining emphasis over the traditional fixed topology of battery pack due to its advantages adapting flexible (series-parallel) during operation in for meeting non-linear time-dependent load requirements. There could emerge serious issues such as those related safety malfunction switching circuit, heat generation from switches frequent circuits...

1 Authors are listed in alphabetical order 2 Mary M. Eshaghian-Wilner is a Patent Agent at the Electronics Practice Group of Foley & Lardner, LLP. She is also an Adjunct Professor of Electrical Engineering at the University of California, Los Angeles. Abstract In this paper, we present a number of parallel and fault-tolerant routing schemes for a set of nanoscale spin-wave architectures. The ar...

The RACE R parallel computer system provides a high-performance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE system, a parallel computer for embedded applications. The topology of the network, which is constructed with 6-port switches, can be specified by the customer, and is typically a fat-tree, a Clos network, or a mesh. T...

Integrated optical switches using mechano-optical sensing are gaining more attention in many fields due to their fast switching speed, large bandwidth and compact devices. In this paper, a micromachined electrostatically actuated metal plate to sense the evanescent field above the waveguide is presented. The feasibility of MEMS based light weight mechanical plates to achieve fast switching is e...

Task scheduling is an important aspect for parallel programming. In this paper, the program to be scheduled is modeled as a Directed Acyclic Graph (DAG), and we target parallel embedded systems of multiple processors connected by buses and switches. This paper presents improvements for list scheduling heuristics with communication contention. We use new node priorities (top level and bottom lev...