This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18m CMOS process. A sample–reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering po...

This article addresses the issue of when to suppress or not to suppress the transmitted carrier in designing a coherent communication system employing a carrier tracking loop for carrier synchronization. Assuming that a phase-locked loop (PLL) is used whenever there exists a residual carrier and a Costas loop is used whenever the carrier is suppressed, the regions of system parameters that deli...

The problem of robust phase-locked loop design has attracted attention for many years, particularly since the advent of the global positioning system. This paper proposes and demonstrates the use of a fuzzy PLL to estimate the time-varying phase of a sinusoidal signal. It is shown via simulation results that fuzzy PLL's offer performance comparable to analytically derived PLL's (e.g. Kalman fil...

In grid-connected inverters (GCIs), the phase-locked loop (PLL) behaves as a negative admittance at point of common coupling (PCC), composed both PLL controller and current terms. Therefore, not only dynamics, but also dynamical interactions between might trigger instabilities in weak grids, which complicates parameters regulation. The smaller bandwidth could help to mitigate instabilities, exp...

Version 4, 1 April 2003 A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that is both accurate and efficient. The methodology begins by characterizing the noise behavior of the blocks that make up the PLL using transistor-level simulation. For each block, the jitter is extracted and provided as a parameter to behavioral models for inclusion in a high-level simulat...

One method to enable fast acquisition of a phase-locked loop (PLL) in spite of large frequency offsets and small PLL bandwidths is to use an additional AFC loop. A suitable frequency error detector (FED) for large frequency offsets is the well-known balanced quadricorrelator. This FED is shown to produce great pattern jitter if it is to work with digital modulated MQAM and MPSK signals (M > 2) ...

Out of various moving average filter (MAF)-based phase-locked-loop (PLL), quasi type-1 PLL (QT1-PLL) is widely adopted due to its fast dynamic performance, implementation simplicity, and harmonics rejection abilities. However, the performance QT1-PLL deteriorates in presence an off-nominal frequency unbalanced grid voltage component. Moreover, sensitivity towards fundamental negative sequence (...

Today, and especially with the growing interest in distributed renewable energy sources (DRESs), modern electric power systems are becoming more complex. In order to increase DRES penetration, grid side converter (GSC) control techniques require appropriate synchronization algorithms that able detect voltage status as fast accurately possible. The drawbacks of published phase-locked loop (PLL) ...

Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors and two duty cycle control buffers a low cost frequency doubler circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input clock signal with an unpredictable duty cycle is inputted to a rising (or falling) edge detector. The edge detector converts the ...

Frequency-modulated continuous-wave (FMCW) radars necessitate fast frequency modulation. However, finite loop bandwidth of a phase-locked (PLL) limits the accuracy This paper proposes phase compensation (PC) technique to address this limitation. The synthesizer PLL with PC realizes and precise triangular chirp modulation by adding compensating square wave before integral path filter. is designe...