BACKGROUND The prevalence of food allergy has been increasing, but treatment is very limited. DNA vaccination has been recognized as a promising method for the treatment of allergic diseases; however, poor immunogenicity has hindered its application. METHODS BALB/c mice were intradermally injected with plasmid DNA encoding the peanut protein Ara h 2 (pAra h 2) or pAra h 2 pretreated with poly...

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm ...

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circ...

This paper discusses a systematic design of a ∑-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of di...

V m f 4 AbstractA phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. . Implemented in 1 .w CMOS, the PLL has a 111-29OMHz range, phase noise of -92.3dBdHz at a 5OkHz offs...

This paper presents a novel phase-locked loop (PLL) structure for improving the transient stability of grid-connected converters by introducing voltage normalization control (VNC) in conventional PLL. First, underlying mechanism losing synchronization during grid fault is analyzed, and it revealed that key factor significant decrease magnitude at point common coupling (PCC). In order to avoid d...

For the development of effective drug carriers, nanocapsules that respond to micro-environmental changes including a decrease in pH and a reductive environment were prepared by the stabilization of polymer vesicles formed from head-tail type polycations, composed of a polyamidoamine dendron head and a poly(L-lysine) tail (PAMAM dendron-PLL), through the introduction of disulfide bonds between t...

Clock recovery circuits are used in data communication systems for the system synchronization. In general a PLL (Phase Locked Loop) circuit is used to extract the clock signal from the input data stream. The recovered clock signal is always jittered and have to be adjusted by using a dejitter circuit. Tracking these errors over an extended period of time determines the system stability. Sources...

This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete Fourier transform (SGDFT) filter-based fundamental positive sequence component separator (FPSCS), the synchronousreference-frame PLL (SRF-PLL)...