Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Ag...

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for realtime spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel–parallel multiplier and two adders. It is capable of computing one butterfly computation e...

In this paper, we present flexible multi-precision multiplier that combined variable precision, parallel processing (PP), razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for variety of operating conditions. All of the building blocks of proposed flexible multiplier can either work as independent small precision multiplier or parallel...

This paper provides a preconditioned iterative technique for the solution of saddle point problems. These problems typically arise in the numerical approximation of partial differential equations by Lagrange multiplier techniques and/or mixed methods. The saddle point problem is reformulated as a symmetric positive definite system, which is then solved by conjugate gradient iteration. Applicati...

This paper describes in detail the design of a custom CMOS Fast Fourier Transform(FFT) processor for computing 256-point complex FFT. The FFT is well suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100ns thus ...

Power consumption has become a critical concern in today’s VLSI system design. The growing market for fast floating-point co-processors, digital signal processing chips, and graphics processor has created a demand for high speed, area-efficient multipliers. The Modified Booth Recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which ...

A 4x4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4x4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus...

A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multipli...

Two’s complement multipliers are important for a wide range of applications. Paper describes a technique to reduce by one row the maximum height of the partial product array generated by Radix-4 Booth’s multiplier, without any increase in the delay of the partial product generation stage. The design of 8 bit and 16 bit multiplication scheme using different types of multiplier like Array multipl...

Multiplier is one of the essential element for all digital systems such as digital signal processors, microprocessors etc. In this paper, a new high speed multiplier using booth recoding technique is presented. This algorithm can be implemented by using the radix-8 booth recoding process. The proposed multiplier reduces the partial product array by almost 3/4 th the size of the bits. This reduc...