1. Introduction Power has become a primary design constraint in digital integrated circuits. Most designs in sub-100nm technologies will either maximize the performance under power constraints or minimize the energy for required amount of computation. To achieve the optimality in power-performance space, integrated circuits have to be optimized at all levels of hierarchy: device, circuit, micro...

In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the ana...

This paper reports a self powered smart sensor node (also called ‘smart tag’) consisting of a piezoelectric vibration energy harvester, a power conditioning circuit, sensors and an RF transmitter. The smart tag has dimensions similar to a credit card and can be easily integrated into various applications such as the ibration energy harvesting iezoelectric generator elf-powered ireless sensor no...

A compact fully integrated wideband six-port device composed of a suspended stripline Wilkinson power divider and three bias stripline of 3-dB quadrature directional couplers is presented. In order to integrate a six-port circuit, a multilayer circuit structure has been adopted by the via hole interconnection at the output port of the divider. The 3-dB quadrature directional coupler is composed...

The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modelin...

High levels of integration in integrated circuits often lead to the problem of running out of pins. Narrow data buses can be used to alleviate this problem provided that the degraded performance due to wait cycles can be tolerated. We address bus coding methods for low-power core-based systems incorporating narrow buses. We show that transition signaling combined with bus-invert coding, which w...