In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM desig...

Progressive supranuclear palsy (PSP) is frequently misdiagnosed as other Parkinsonism because of clinical heterogeneity of PSP. We present here a case of a 67-year-old male patient with frontotemporal dementia-like cognitive impairment including language difficulties and abnormal behaviors. He showed severe facial dystonia after the levodopa treatment. Herein, we describe an unusual case of a p...

We describe the design of an embedded 128-Kb Silicon-OnInsulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25m fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presen...

Silicon-on-insulator (SOI) wafers are nowadays being prominently used for the manufacture of new generation semiconductor devices. In order to maximize the device yield, the device industry is seeking SOI wafers that meet very stringent wafer specifications such as very low wafer bow and warp. An SOI wafer can undergo severe process-induced stresses during its manufacture leading to significant...

The interplay of exchange correlations and spin-orbit interaction (SOI) on the many-body spectrum of a copper phtalocyanine (CuPc) molecule and their signatures in transport are investigated. We first derive a minimal model Hamiltonian in a basis of frontier orbitals that is able to reproduce experimentally observed singlet-triplet splittings. In a second step SOI effects are included perturbat...

An optimum design with silicon-on-insulator (SOI) device structure was proposed to eliminate back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) and to improve breakdown voltage. The SOI structure was characterized by low doping buried layer (LDBL) inserted between the silicon layer and the buried oxide layer. The LDBL thickness is a...

In recent years, the mobile communication market represented by the mobile telephone has been showing remarkable growth. This market has been making tough demands for semiconductor integrated circuits, which are mounted components, to consume less power, have higher integration, have multi-function capability, and be faster. We at Oki have been working on developing complete depletion type SOI ...

FULLY DEPLETED (FD) SILICON ON INSULATOR (SOI) METAL OXIDE FIELD EFFECT TRANSISTOR (MOSFET) IS THE LEADING CONTENDER FOR SUB 65NM REGIME. THIS PAPER PRESENTS A STUDY OF EFFECTS OF WORK FUNCTIONS OF METAL GATE ON THE PERFORMANCE OF FD-SOI MOSFET. SENTAURUS TCAD SIMULATION TOOL IS USED TO INVESTIGATE THE EFFECT OF WORK FUNCTION OF GATES ON THE PERFORMANCE FD-SOI MOSFET. SPECIFIC CHANNEL LENGTH OF...

Recent trends in device design bring a need for SOI wafers with ultra thin BOX below 100A. Difficulties in production of UTBOX SOI wafer by the Smart CutTM technology are highlighted. New process of internal BOX dissolution allows to overcome interface defectivity problems and results in high quality UTBOX and DSB wafers. Mechanism of internal BOX dissolution is presented together with the resu...