In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...

MOS current mode logic (MCML) techniques are usually used for high-speed applications such as high speed processors and multiplexers for optical transceivers. A new design of full adder is proposed based on MOS Current Mode Logic (MCML). It is a new alternative for designing a full adder. Using MCML logic, the power consumptions of circuits can be reduced to the effective level by supplying it ...

An adder is a digital circuit that performs addition of numbers and it plays an important role in today’s digital world. In processors and other kinds of computing devices, Adders are used in the arithmetic logic units. They are also utilized in other parts of the processors for calculating addresses, table indices, increment and decrement operations and other similar operations because it is t...

Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis-based gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of what is the group size maximizing the ...

Among various testing methodologies, Built-in SelfTest (BIST) is recognized as a low cost, effective paradigm. Also, full adders are one of the basic building blocks of most arithmetic circuits in all processing units. In this paper, an optimized testable 2bit full adder as a test building block is proposed. Then, a BIST procedure is introduced to scale up the building block and to generate a s...

We present eight new designs for 1-bit full adder cell featuring hybrid CMOS logic style. These designs are based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP. The new full-adder designs are also categorized in three main categories depending upon the implementation of the logic expre...

multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and reduce the...

Full adders are essentially used as a building block in all arithmetic, DSP and microprocessor applications. In this paper, a 15 transistor hybrid PTL-TG full adder circuit is proposed. The main objective is to provide high speed, low power, full swing operation with good drivability. The choice of logic design affects the circuit performance. The delay time depends on the number of transistors...