An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists in increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor nor the delay of an iteration. As a consequence, for some values of the ...

A Radix-4 Quasi-cyclic shift network (QSN) for reconfigurable QC-LDPC decoders is presented in this paper. A complexity reduction technique is described to reduce the total gate count at each stage in addition to the fact that Radix-4 logarithmic barrel shifter naturally offers less number of stages compared to Radix-2. The proposed Radix-4 QSN architecture supports various code rates and all s...

Digit-recurrence binary dividers are sped up via two complementary methods: keeping the partial remainder in redundant form and selecting the quotient digits in a radix higher than 2. Use of a redundant partial remainder replaces the standard addition in each cycle by a carry-free addition, thus making the cycles shorter. Deriving the quotient in high radix reduces the number of cycles (by a fa...

In this paper, we propose a new efficient reverse converter for the 4-moduli set { 2, 2 + 1, 2 − 1, 2 − 1 } based on a modified Chinese Remainder Theorem and Mixed Radix Conversion. Additionally, the resulting architecture is further reduced to obtain a reverse converter that utilizes only carry save adders, a multiplexer and carry propagate adders. The proposed converter has an area cost of (1...

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

In this paper we propose a homomorphic encryption-based secure electronic voting scheme that is based on [5]. It guarantees eligibility, unreusability, privacy, verifiability and also receipt-freeness and uncoercibility. The scheme can be implemented in a practical environment, since it does not use voting booth or untappable channel, only anonymous channels are applied.

Fast Fourier Transform (FFT) processors employed with pipeline architecture consist of series of Processing Elements (PE) or Butterfly Units (BU). BU or PE of FFT performs multiplication and addition on complex numbers. This paper proposes a single BU to compute radix-2, 8 point FFT in the time domain as well as frequency domain by replacing a series of PEs. This BU comprises of fused floating ...

VAES stands for variable AES. VAES3 is the third generation format-preserving encryption algorithm that was developed in a report [4] simultaneously with the comprehensive paper on FPE [1] and subsequently updated slightly to be in concert with the FFX standard proposal. The standard proposal of FFX includes, in an appendix, example instantiations called A2 and A10. A follow on addendum [3] inc...

FFT/IFFT has been one of the most important algorithms in digital signal processing. In the recent years, the FFT/IFFT has frequently been applied in the modern communication systems due to its efficiency for OFDM (Orthogonal Frequency Division Multiplex) implementation. Many applications, like xDSL modems, HDTV, mobile radio terminals, use FFT/IFFT processor as a key component. The butterfly e...