We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signiicantly reducing the number of injected faults and faulty-event evaluations. Speciically, we dynamically reduce injection of two types of faults: (1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a ip-op or primary ou...

In this paper, we propose a new high-level test pattern generation technique for sequential circuits. The main motivation is two-fold: on one hand, we elaborate test data for design validation; on the other hand, we deal with the problem of structural test development at functional level. The proposed test method, i.e. mutation testing, allows us to work with a fault model at software level on ...

Boolean circuits of polynomial size and poly-logarithmic depth are given for computing the Hermite and Smith normal forms of polynomial matrices over finite fields and the field of rational numbers. The circuits for the Smith normal form computation are probabilistic ones and also determine very efficient sequential algorithms. Furthermore, we give a polynomial-time deterministic sequential alg...

The feasibility of generating high quality functional test vectors f o r sequential circuits using the Growth (G) and Disappearance ( 0 ) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model b y proving the ability of this model t o guarantee complete stuck fault coverage an combinational and sequential circuits synthesized empl...