K. Olivier, J.E. Cilliers and M. du Plessis The test and evaluation of modern radars using hardware in the loop (HIL) simulators requires the use of wideband, high fidelity, digital radio frequency memories (DRFM) in order to generate realistic target returns. This paper highlights important aspects of wideband DRFM design on printed circuit board (PCB) and also presents the architecture of the...

Neuromorphic vision processor is an electronic implementation of vision algorithm processor on semiconductor. To image the world, a low-power CMOS image sensor array is required in the vision processor. The image sensor array is typically formed through photo diodes and analog to digital converter (ADC). To achieve low power acquisition, a low-power mid-resolution ADC is necessary. In this pape...

A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time cons...

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this work. The structure proposed ADC based on the sub-ranging which a 4-bit resolution flash-ADC utilized. designed by employing comparator equipped with common mode current feedback gain boosting technique (CMFD-GB) residue amplifier. 8 bits can achieve speed 140 megasamples per second. at 10 MHz...

Abstract This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator mismatch that degrades linearity of high‐resolution SAR ADC. reduced within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid ...

Abstract With the development of communication technology, performance digital-to-analog converters as last link in signal processing is particularly important. This paper analyzes errors current rudder DAC and their effect on performance. Different compensation methods are proposed to compensate for or eliminate errors. Through system modeling, it concluded that under conditions static paramet...

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed low technique i.e., DTMOS logic. It consists of R-2R DAC, low-power comparator, digital logic low-leakage. The designed comparator is differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created proper operation remain in saturation and ...