Optical slot waveguides fabricated on the silicon-on-insulator (SOI) platform enables direct light–matter interaction [1]. Its ring resonators are promising for trace-gas sensing [2], microparticle trapping [3], and nano-optomechanical mass and displacement measurements [4]. To date, slot ring/racetrack structures on buried oxide (BOX) have been adopted in the above applications. However, their...

The three-dimensional (3D) integrated circuit technology developed by MIT Lincoln Laboratory allows circuit structure that forms on several silicon-on-insulator (SOI) substrates to be integrated into a 3D integrated circuit. This 3D technology gives the possibility of better thermal and noise management, more compact design, and so on. However, circuit design in the 3D technology has not been f...

We present a design of a vision sensor device, implemented in a three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. The proof-of-concept device contains an image sensor array on one layer, and a pitchmatched array of 32x32 pixel-parallel processors, distributed over two further layers. The processor array uses mixed-mode processing elements and operates in SIMD (Single Inst...

The fundamental properties of valleys are recently attracting growing attention due to electrons in new and topical materials possessing this degree-of-freedom and recent proposals for valleytronics devices. In silicon MOSFETs, the interest has a longer history since the valley degree of freedom had been identified as a key parameter in the observation of the controversial "metallic behaviour" ...

The fabrication and characterization of SiGeC cantilever microcoolers are described. Silicon on insulator (SOI) was used as the substrate, and two layers of 3 μm p-SiGe0.07C0.0075 and 1.14 μm n-SiGe0.07C0.0075 lattice matched to silicon were grown using molecular beam epitaxy. The uni couple cooler was fabricated using conventional integrated circuit (IC) processing, and the cantilever structur...

The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm are simulated. Simulations show that with a fixed channel length, when the gate length is increased, the output drain current characteristics slope is increas...

Light emitting pn-diodes were fabricated on a 5.8 mm thick n-type Si device layer of a silicon-on-insulator (SOI) wafer using standard silicon technology and boron implantation. The thickness of the Si device layer was reduced to 1.3 mm, corresponding to a 4l-cavity for l 1⁄4 1150 nm light. Electroluminescence spectra of these low Q-factor microcavities are presented. Addition of Si/SiO2 Bragg ...

Polarization insensitive wavelength conversion of a 40 Gb/s non-return-to-zero (NRZ) differential phase-shift keying (DPSK) data signal is demonstrated using four-wave mixing (FWM) in a silicon nanowire circuit. Polarization independence is achieved using a diversity circuit based on polarization rotators and splitters, which is fabricated by a simple process on the silicon-on-insulator (SOI) p...

In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reducti...