Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are characterized by the th power law model. In order to emphasize the nonlinear behavior of a CMOS inverter, the interconnect is modeled as a lumped load. The propagation delay of a CMOS inverter is characterized for...

SPICE is a widely used tool for simulation of analog circuits. Accurate models of devices are crucial for obtaining realistic results from the simulation. Many devices must still be modelled with subcircuit models in order to achieve sufficient accuracy. Parameter values for subcircuit elements are determined by optimisation. Use of SPICE OPUS optimisation capabilities for model parameter ident...

Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. We develop an analytical delay model to incorporate inductance eeects into the delay estima...

The Capability Maturity Model and SPICE approach to software process improvement has resulted in a robust system for improving development process capability in the field of software engineering. We apply these same ideas in the area of e-learning in order to explore whether similar insights could be generated for institutions engaged in online delivery of teaching. In order to test this idea, ...