The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design. It has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), which is much hi...

Due to the limited access to the individual embedded cores in System-on-Chips (SoCs), testing is more time consuming and costly than testing standalone Field Programmable Gate Arrays (FPGAs). However, the ability for an embedded processor core to reconfigure FPGA cores in SoC applications opens new opportunities for Built-In Self-Test (BIST) of the FPGA cores themselves. This paper discusses a ...

This paper presents a logic BIST approach which combines deterministic logic BIST with test point insertion. Test points are inserted to obtain a first testability improvement, and next a deterministic pattern generator is added to increase the fault efficiency up to 100%. The silicon cell area for the combined approach is smaller than for approaches that apply a deterministic pattern generator...

A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given since only a two-pattern test set is required as input.

Pseudorandom built-in self test (BIST) generators have been widely utilized to test integrated circuit and systems. In this Project an accumulator-based-3 weight test pattern generation scheme is presented and proposed scheme generates set of test patterns with weights 0, 0.5 and 1. These accumulators are mostly found in current VLSI chips and that the scheme can be efficiently to drive the har...

We present an embedded processor based approach for Built-In Self-Test (BIST) and diagnosis of programmable logic and memory resources in Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs), large random access memories (RAMs), and digital signal processors (DSPs) in all of their modes of operation. The approach is applicable to any FPGA...

In this paper, a cost-efficient fault-tolerant router design, called 20-Path Router (20PR) architecture, is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. The 20PR consists of two fault-tolerant circuits: 1) a Builtin Self-Test and Self-Diagnosis (BIST/SD) circuit to detect and locate faulty FIFOs and MUXs, and 2) a Fault-Isolation (FI) circuit t...

Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection latency since it is not until the signatures are scanned out and compared off-chip that a fault become apparent. Aliasing, which is a fallout of long detection latency, is a ser...

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness ...

A complex SoC typically consists of numerous of memories in today's digital systems. This paper presents a test/ repair flow based on memory grouping strategy and a revised distributed BIST structure for complex SoC devices. A gated selecting method is added to the distributed BIST structure. Also, this paper for the first time proposes a robust post repair stage based on BIRA and memory groupi...