The increasing complexity of algorithms and embedded systems constraints has lead to advanced design methodologies. Hardware/Software co-design methodology has made it possible to find an optimal architecture for a given application by exploring the design space before building a real hardware prototype. The Design Space Exploration is basically exploring the various processor architectures in ...

A common approach to enhance the performance of processors is to increase the number of function units which operate concurrently. We observe this development in all recent superscalar and VLIW (very long instruction word) processors. VLIWs are easier extensible to high performance ranges because they lack much of the superscalar hardware required for dependence checking and hardware resource a...

As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isom...

Synchronous Transfer Architecture (STA) is a coarse-grain reconfigurable hardware. It is modelled by using a common machine description that is suitable for both compiler and core generator. STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for such ISA needs highly optimizing techniques...

We identify and analyze different classes of schedules for VLIW processors. The classes are induced by various common techniques for generating or enumerating them, such as integer linear programming or list scheduling with backtracking. In particular, we study the relationship between VLIW schedules and their equivalent linearized forms (which may be used, e.g., with superscalar processors), a...

We have in the past investigated the design and implementation of micronet-based architectures of the scalar[AR94], superscalar[AM99], VLIW[AS97] and Multithreaded[AHKR01] kind, which were all based on a RISC-like instruction set. In this paper, we present a preliminary design, based around a micronet core, of an asynchronous Complex Instruction Set Computer (CISC) architecture. A TRANSLATOR mo...

The design of an application-specific parallel architecture implementing a new image compression Mgorithm is described. This algorithm, developed by Jos~ Moura and Nikhil BMram, achieves a higher compression ratio than the JPEG algorithm for a given image quality. The goal of this project is to design a processor which can compress 256 × 256 8-bit monochrome images at a rate of 30 frames per se...

 To achieve performance, Explicitly Parallel Instruction Computing (EPIC) systems take the responsibility of extracting instruction-level parallelism (ILP) from the hardware and give it to the compiler. They expose a large part of the hardware control at the conventional machine level. Dynamically Trace Scheduled VLIW (DTSVLIW) systems, on the other hand, leave the responsibility of extracting...

SO, WON. Software Thread Integration for Converting TLP to ILP on VLIW/EPIC Architectures. (Under the direction of Alexander G. Dean.) Multimedia applications are pervasive in modern systems. They generally require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor makers to adopt high-performance architectures like...

Clustered organizations are becoming a common trend in the design of VLIW architectures. In this work we propose a novel modulo scheduling approach for such architectures. The proposed technique performs the cluster assignment and the instruction scheduling in a single pass, which is shown to be more effective than doing first the assignment and later the scheduling. We also show that loop unro...