A wireless ad hoc network typically refers to any set of wireless networks where all devices have equal status on a network and are free to associate with any other wireless ad hoc network devices in their range. As the nature of these networks, they commonly do not have external power supplies, and each node has a limited internal power source. In this paper, we put forward a new routing proto...

Aiming at the problem of intelligent monitoring in grain storage, a design plan of temperature and humidity is proposed based on ZigBee wireless network. The system integrates the SCM technology, computer technology, intelligent sensor technology and wireless communication technology, using STC89C52 microcontroller as the control chip, SHT11 as an integrated temperature and humidity sensor, and...

In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting both similarities and differences between NoCs and traditional networks. As an initial case study, we examine network congestion in bufferless NoCs. We show that congestion manifests itself differently in a NoC than in a traditional network. This both reduces system throughput in c...

Networks-on-chip (NoC) have been used as an interesting option in design of communication infrastructures for embedded systems, providing a scalable structure and balancing the communication between cores. Because several data packets can be transmitted simultaneously through the network, an efficient routing strategy must be used in order to avoid congestion delays. In this paper, ant colony a...

A true application-specific Network-on-Chip (NoC) requires the exact knowledge of the internal traffic behavior during the NoC is fully running the target application. Therefore, an accurate traffic measuring method is necessary. In this work, a simple but powerful traffic monitoring system is presented for the accurate evaluation and refinement of an application-specific NoC. The traffic monit...

Since around year 2000, Network-on-Chip (NoC) has been proposed as a global communication paradigm to interconnect tens or hundreds of cores on a single chip (Bjerregaard & Mahadevan, 2006). One key challenge for NoCs has been Quality of Service (QoS), which is concerned about performance guarantees or bounds. To achieve QoS, formal performance analysis is essential because it overcomes the unc...

This paper presents present three novel buffer schemes for system on chip applications that have an interconnection network. The proposed schemes are based on a DAMQ self-compacting buffer to provide larger available buffer space per channel for incoming flits. The proposed schemes outperform existing approaches, and optimize buffer management by providing better throughput when the network has...

NoC (network On Chip) is an efficient approach to design the communication subsystem between IP Cores in SoC (System On Chip). In this paper a communication infrastructure design using CDMA (Code division multiple access) based shared bus architecture for core-to-core communication in NoC is presented. CDMA has been proposed as an alternative way for interconnect of IP cores in a SoC design, or...

Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-onChip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systemson-chip (SoC) design. ...