Maximal length Feedback with Carry Shift Register sequences have several remarkable statistical properties. Among them is the property that the arithmetic correlations between any two cyclically distinct decimations are precisely zero. It is open, however, whether all such pairs of decimations are indeed cyclically distinct. In this paper we show that the set of distinct decimations is large an...

Abstract The rise of persistent memory is disrupting computing to its core. Our work aims help programmers navigate this brave new world by providing a program logic for reasoning about x86 code that uses low-level operations such as accesses and fences, well persistency primitives flushes. logic, Pierogi , benefits from simple underlying operational semantics based on views able handle optimis...

A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever diier, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2 log N bits each and guarantees convergence to identical values within N 2 \triggers".

This rough diamond presents a new domain-specific language (DSL) for producing detailed models of Instruction Set Architectures, such as ARM and x86. The language’s design and methodology is discussed and we propose future plans for this work. Feedback is sought from the wider theorem proving community in helping establish future directions for this project. A parser and interpreter for the DSL...

We study complexity issues related to the model-checking problem for LTL with registers (a.k.a. freeze LTL) over one-counter automata. We consider several classes of one-counter automata (mainly deterministic vs. nondeterministic) and several syntactic fragments (restriction on the number of registers and on the use of propositional variables for control locations). The logic has the ability to...

Dynamic binary translation has a history of being used to ease transitions betweenCPU architectures[7], includingmicro-architectures. Modern x86 CPUs, while maintaining binary compatibility with their legacy CISC instruction set, have internal micro-architectures that resemble RISC. High performance x86micro-architectures have long used a CISC decoder front-end to crack complex instructions int...

First, three successful environments for artificial evolution in computer systems are analysed briefly. The organism in these enviroment are in a virtual machine with special chemistries. Two key-features are found to be very robust under mutations: Non-direct addressing and separation of instruction and argument. In contrast, the x86 instruction set is very brittle under mutations, thus not ab...

A major hurdle of recent x86 superscalar processor designs is limited instruction issue rate due to the overly complex x86 instruction formats. To alleviate this problem, the machine states must be preserved and the instruction address routing paths must be simplified. We propose an instruction address queue, whose queue size has been estimated to handle saving of instruction addresses with thr...

Developing countries have embarked on the promotion of “ICT access for all” through subsidized Information and Communication Technologies (ICTs), especially in underserviced areas of such countries. The main aim of the “ICT access for all” is to extend the communication services to the large areas of underserviced regions through subsidized communication services. In some instances, subsidies m...