Abstract Since 2001, the IEEE P1581 working group aims to provide a test standard for memories that cannot have boundary-scan. This P1581 activity focuses on test access and test circuitry. This paper elaborates on the status of the draft standard. It describes the test circuitry and an economic model for users of P1581 devices is presented. Currently, the working group is facing a lack of inte...

This paper presents an implemented system for modifying digital circuit designs to enhance testability. The key contributions of the work are: (1) setting design for testability in the context of test generation, (2) using failures during test generation to focus on testability problems, (3) indexing from these failures to a set of suggested circuit modifications. This approach does not add tes...

A diagnosis technique is presented to locate at least one fault in a scan chain with multiple timing faults. This diagnosis technique applies Single Excitation (SE) patterns of which only one bit can be flipped even in the presence of multiple faults. By applying the SE patterns, the problem of simulations with unknown values is eliminated. The diagnosis result is therefore deterministic, not p...

Attempts to commercialize GaN VCSELs have been unsuccessful to date due to the challenges of manufacturability of DBR mirrors, difficulties associated with current blocking, and the complexity of laser liftoff. The new process flow overcomes all three challenges enabling the manufacturing of IIINitride VCSEL without liftoff and with much reduced complexity and the possibility of on-wafer testing.

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Contents This paper describes strategies for functional testing of graphical user interfaces (GUIs) and web-based applications because these activities are manually intensive and a costly problem. Tools exist for regression testing of interface functionality through capture/playback mechanisms, but this approach is manually intensive and difficult to maintain. There are better ways to design fo...

Software testing is normally used to check the validity of a program. Test oracle performs an important role in software testing. The focus in this research is to perform class level test by introducing a testing framework. A technique is developed to generate test oracle for specification-based software testing using Vienna Development Method (VDM++) formal language. A three stage translation ...

Testing a secure system is often considered as a severe bottleneck. While testability requires to an increase in both observability and controllability, secure chips are designed with the reverse in mind, limiting access to chip content and on-chip controllability functions. As a result, using usual design for testability techniques when designing secure ICs may seriously decrease the level of ...