The design of an N -comparator based asynchronous Successive Approximation Analog-to-Digital Converter (SAR ADC) is described (with N = 6) working at 20 MS/s and consuming only 5.6 mW for low power high speed applications like communication systems. Resetting the comparators in each conversion cycle is avoided (reducing power consumption compared to [1]) and only N latches are used overall (inc...

We have designed, fabricated and tested the second-generation (2G) design of a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC chip uses the phase modulation–demodulation architecture and on-chip digital filtering. The 2G ADC design has been substantially enhanced. Both ADC front-end modulator and demodulator, as wel...

Microcontrollers are emerging into new applications like smart phones, audio accessories, video gaming peripherals and advanced medical devices, providing highperformance, reliability and low-power consumption for end users. In this paper the design of a microcontroller-based hearing aid device is provided, by which power consumption and hardware area are reduced. The proposed digital hearing a...

Abstract— A probe system has been developed on the basis of an external ADC/DAC module (ADC is analog-to-digital converter and DAC digital-to-analog converter). Using this system, it possible to determine all main plasma parameters continuous pulsed gas discharges. program for Windows operating in C++ control system. The can be used diagnostics devices included modern microplasma analyzers mixt...

The Transition Radiation Detector (TRD) of the ALICE experiment at CERN incorporates 1.2 million channels which are individually read out and processed. The front-end electronics (FEE) utilizes two custom chips: an 18 channel analog preamplifier and shaper (PASA) and a mixed-signal chip, performing 10 bit analog-to-digital conversion, event buffering and local tracking (TRAP). Both chips togeth...

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The A...

In this paper, a differential cyclic analog-to-digital converter based in switched-capacitor techniques is presented. This approach allows a reduced die size and achieves a higher precision, making this circuit suitable to low speed measurements, such electric energy meter systems where a minimum sampling rate of 1,200 samples per second is required for 2-channel systems (single-phase) and 7,60...

The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of lo...

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this ca...