High Level CMOS power estimation requires the application of real system inputs to determine the power rating of a new application specific integrated circuit. The production of this data implies the ability to produce inputs before the design has been completed. Where a device functions in an environment with software, an assembler or compiler must already exist. This is often not the case, as...

This paper proposes a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator’s...

Traditionally, focal plane arrays require extensive external focal plane electronics (FPE) to provide clocks and biases as well as to digitize the analog output signals. The FPE has to be well-designed and is typically large, heavy and powerhungry. Most importantly, the FPE has to be placed some distance away from the FPA, which complicates maintaining low noise performance throughout the compl...

This paper addresses the impact of near-end crosstalk on the signal integrity of two coupled microstriplines. The physical mechanisms that lead to near-end crosstalk are discussed in detail, and results from computer simulations are highlighted to provide some insight into this kind of signal degradation. The load for each microstripline is an application specific integrated circuit (ASIC) with...

In this paper are described simulation and measurement processes of a power switch cell used for single event latchup protection of a digital fault tolerant application specific integrated circuit. The standard IHP 250 nm simulation models of components are used for the performed analog simulation using the Virtuoso Cadence tools.

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the f...

3D stacking of dies is an enabler for further miniaturization and increase of functionality. Individual dies are thinned down aggressively – down to approximately 20 um – and glued on top of each other. With such 3D ICs, the same power dissipation will lead to higher temperatures in a stacked-die package compared to a single-die package. Hence, there is a need to perform detailed thermal analys...

• Identification of the optimum technology and layout of the tracking detectors for the upgraded ATLAS ID and construction of a short-strip silicon detector (SSD) module with sufficient radiation hardness for the intermediate and outer tracking region in the upgraded ATLAS ID. • Evaluation of integrated circuit technologies for the readout of the upgraded ATLAS ID, in particular the evaluation ...

Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry strength. Nonetheless, it is possible to overcome these issues. This paper describes the courses in these areas at the University of Canterbury, including a practical IC design project that has been running successful...

In this paper, we present our quantitative studies of the impact of 3D IC design on repeater usage. The repeater usage is estimated by the interconnect optimizer IPEM in the post-placement/ pre-routing stage, where the 2D and 3D placement are generated by state-of-art mixed-size placers mPL6 and mPL-3D. Experiments on a set of real industrial designs show that, through 3D placement, the total n...