This paper addresses the problem of synthesizing an asynchronous system from a temporal specification. We show that the cost of synthesizing a single-process implementation is the same for synchronous and asynchronous systems (2EXPTIME-complete for CTL* and EXPTIME-complete for the μ-calculus) if we assume a full scheduler (i.e., a scheduler that allows every possible scheduling), and exponenti...

Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Firstly, the previously required local ring oscillators are avoided. Instead, an external clock with arbitrary phase for each GALS block is used. Details of the required wrapper circuitry, the proposed design flow and performance...

A framework for evaluating the performance of asynchronous systems is presented. Performance evaluation of the asynchronous circuits is a challenging process due to the dependencies between highly concurrent events. The utilized performance model is a Probabilistic Timed Petri-Net (PTPN) with possible choice places to capture the conditional behavior of the system. The proposed framework exploi...

There are several methods of describing systems in a modular fashion. These descriptions may represent a system in one of several ways, for example in a text form or as a graph. By using a modular representation, a large system can be split into multiple smaller sections, which can make operations such as verification of a system simpler and quicker. Multiple methods of designing asynchronous c...

The asynchronous systems are the non-deterministic models of the asynchronous circuits from the digital electrical engineering, where non-determinism is a consequence of the fact that modelling is made in the presence of unknown and variable parameters. Such a system is a multi-valued function f that assigns to an (admissible) input u : R! f0; 1gm a set f(u) of (possible) states x : R! f0; 1gn:...

This paper addresses an alternative approach to detecting the completion of computation in asynchronous digital circuits. Presented method, as the name suggests, is based on sensing the amount of current drawn by the combinatorial logic and exploits the behavior of CMOS logic gates for separating the computation state from the idle state. The paper deals with the current sensor design, its impl...

As the number of transistors on a single integrated circuit approach a billion, the problems of clock distribution, power consumption, multiple clock domains, meeting timing requirements, and reuse of subsystem designs grow ever more difficult. Coordinating a billion transistors with the present design methodologies will require hundreds of years of engineering time. A new design methodology is...

Based on PAFAS (Process Algebra for Faster Asynchronous Systems), a testing-based fasterthan relation has previously been developed that compares the worst-case efficiency of asynchronous systems. This approach reveals that pipelining does not improve efficiency in general; that it does so in practice depends on assumptions about the user behaviour. As a case study for testing under such assump...

Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a di cult and error-prone task. An adequate synthesis method will signi cantly simplify the design and reduce errors. In this paper, we present a general and e cient partitioning approach to the synthesis of asynchronous circuits...

We characterize the user capacity, i.e., the maximum number of supportable users at a common SIR target level for a fixed processing gain, of a single-cell symbol asynchronous CDMA system. We show that the user capacity of an asynchronous system is the same as the user capacity of a synchronous system; that is there is no loss in user capacity due to asynchrony. Optimum signature sequences are ...