To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SAT-based strategies for the verification and synthesis of selfchecking circuits p...

We propose a new test application method that can be applied on top of any combinational stuck-at fault ATPG to significantly reduce the test application time in full scan designs. In contrast to any other existing method, our approach effectively utilizes both the shift and reapply basic scan operations. The computational difficulties that arise due to the enormous search space are tackled by ...

In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injec...

We introduce a formal mechanism for capturing test justification and propagation related behavior of blocks. Based on the identified test translation behavior, an RTL testability analysis methodology for hierarchical designs is derived. An algorithm for pinpointing the local-to-global test translation controllability and observability bottlenecks is presented. The analysis results are validated...

This study presents a Fault Tolerant memory cores based on the property of Component Reusability, a method for Fault Tolerance for content addressable memories. The memories used in the design are 256, 512, 1024 and 2048 bytes. The fault is injected into the circuitry operation by using Automatic Test Pattern Generators (ATPGs). The design has been implemented in Cadence 90 nm technology and te...

Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establ...

Model-based diagnostic reasoning often leads to a large number of diagnostic hypotheses. The set of diagnoses can be reduced by taking into account extra observations (passive monitoring), measuring additional variables (probing) or executing additional tests (sequential diagnosis/test sequencing). In this paper we combine the above approaches with techniques from Automated Test Pattern Generat...

Y.-M. Jiang is with the Synopsys, Mountain View, CA 94043 USA. A. Krstic and K.-T. (Tim) Cheng are with the University of California, Santa Barbara, CA 93106 USA. This work was supported by the Synopsys, NEC USA, and California MICRO program. Abstract We present new techniques for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. We investigate four ...

Current paper describes a new environment MOSCITO for providing access to tools over the internet. The environment is built according to the master-slave concept, and it allows to encapsulate different EDA tools in order to form various work flows. In this paper we discuss integration of two systems for digital test into the MOSCITO environment. The first one is a hierarchical system DECIDER, w...

In the past years, researchers have published tens of papers whose title was including the magic words “high-level ATPG” or something similar. However, high-level ATPG tools are hardly available on the market, and industries still demand for effective solutions in this area. Why? What would be necessary in order to change this situation? To answer, we should try to compare what has been propose...