Automatic assessment of programming exercises is typically based on testing approach. Most automatic assessment frameworks execute tests and evaluate test results automatically, but the test data generation is not automated. No matter that automatic test data generation techniques and tools are available. We have researched how the Java PathFinder software model checker can be adopted to the sp...

This paper describes a tool which assists the designer in the rapid generation offunctional tests for mixed-signal circuits down to the actual testsignals for the tester. The tool is based on manipulating design data, making use of macrobased test libraries and tester resources provided by the test engineer, and computer-based interaction with the designer.

Logical reversibility is the basis for emerging technologies like quantum computing, may be used for certain aspects of low-power design, and has been proven beneficial for the design of encoding/decoding devices. Testing of circuits has been a major concern to verify the integrity of the implementation of the circuit. In this paper, we propose the main ideas of an ATPG method for detecting two...

This paper deals with the problem of automated test pattern generation for large digital circuits. A distributed approach based on Genetic Algorithms is presented, which exploits the computational power of workstation networks to solve the problem even for the largest circuits. A prototypical system named GATTO is presented: the experimental results show that good results can be reached with CP...

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract The gate level techniques are used in simulation to identify ISE’s and also these techniques are implemented based on Sequential Automatic Test Pattern Generation (ATPG). But now a day’s IC’s are very complex so by using above gate level method, it...

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression r...

We present X-tolerant deterministic BIST (XDBIST), a novel method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. Our method allows test patterns to have any number of unknown values with no degradation in compression and application efficiency. XDBIST does not require changing the core logic of th...

The efficiency of pseudo-exhaustive test generation is strictly limited by the maximal number of inputs to be enumerated, since n inputs require a test length of 2n . In contrast to other approaches, the proposed self-test method also takes the fault model into account. In addition to the conventionally used structural circuit information, so-called "functional independencies" can be computed. ...