In the course of this thesis a novel approach for the on-chip generation of a fault-tolerant clock is developed. At first this is motivated by the fact that with shrinking feature sizes and the accompanying increase of transient failure rates it is more and more desirable to provide VLSI (Very Large Scale Integration) circuits that incorporate mechanisms for fault tolerance. In particular, the ...

| The clock tree of modern synchronous VLSI circuits can consume as much as 50% of their entire power budget. Diierent methods of decreasing clock power dis-sipation have been proposed based on low-voltage swings, double-edge triggered ip-ops, gated clocks, etc. In this paper we propose two types of full-swing low-power CMOS clock drivers. Both are based on a stepped charging and discharging of...

This paper summarizes recent research at the author’s laboratory into power management circuitry, including: (1) Envelope-tracking power supplies for base station power amplifiers, (2) Digital PWM generator circuitry, (3) Spreadspectrum clocking for EMI reduction in digitally-controlled power supplies, (4) High-efficiency coupled-inductor DC-DC converters with fast response and low ripple, and ...

An overview of clocking and design of clocked storage elements is presented. Systematic design of Flip-Flop is explained as well as “time borrowing” and absorption of clock uncertainties. We show how should different clocked storage elements be compared against each other. The issues related to power consumption and low-power design are presented.