This paper provides a comparative study of the proposed global clock distribution methods for high-speed digital integrated circuits. Both non-networked and distributed schemes such as travelling and standing wave clock distributions have been reviewed. Performance metrics are described and qualitatively discussed and non-networked approaches were simulated in a low-power 65nm CMOS process.

VARI 2013 was the fourth European workshop on CMOS Variability. The VARI meeting answers to the need to have a European event on variability, where industry and academia meet to discuss. VARI 2013 was organized by the Karlsruhe Institute of Technology (KIT), in Germany. The objective of VARI is to provide a forum to discuss and investigate the CMOS variability problems in methodologies and tool...

The need for faster circuits in smaller area with lower power dissipation has made it a common practice to use the domino CMOS in high performance integrated circuits. However this improved performance comes at the cost of lower noise immunity. Also current trends in integrated circuit technology have increased chances of crosstalk due to capacitive coupling. Though several works have investiga...

Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing "contact resistance" between them, both of which lead to degrading performance and rising energy consumption. Graphene-based transistors and interconnects are a promising nanoscale technology that could potentially address i...

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-lm CMOS technology to achieve 1-kV CDM ESD robustness. 2007 Elsevier Ltd. All rights reserved.

This paper presents the results obtained with a specific test mask designed at Motorola for the study of the electromagnetic parasitic emissions in integrated circuits (IC). First, origins of parasitic emissions are presented for CMOS circuits, and electromagnetic compatibility (EMC) measurements of IC emissions are detailed: a radiated measurement method with respect to the IEC61967-2 standard...

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (C...

In this paper we describe a new architecture of a frequcncy-lo-voltage convcrtcr VVC) :md iLs high frequency intcgrated applications. The circuit is of a rcduccd complexity and its CMOS implcmcnlalion requires a very small area. Besides its small integration arca, thc circuit is vcry fast and has many inlcrcsting high frequcncy applications. This FVC is used to build an integrated high-precisio...

Analog and mixed-signal integrated circuits are rapidly becoming more complex. In addition to the traditional problems associated with testing ICs, such as limited controllability and observability, analog and mixed-signal test is vulnerable to measurement induced errors. Constraints on measuring analog signals signiicantly increase the complexity and cost of testers for such circuits. In this ...