A 2.4GHz low noise amplifier has been designed in a standard CMOS 0.35 urn process. The transistor model is Bsim3 for 0.35um process. The amplifier provides a forward gain of 33dB with a noise figure only 0.92dB while drawing 17mw from a 1.5 V supply. Design simulation results are presented in this paper.

Low noise amplifier when simulated for system level configuration, the scattering matrix in general and scattering parameters in specific play vital role in performance of low noise amplifier for various frequency bands. In this paper the scattering parameter performance was analysed for S-band for recent process technologies available for CMOS and BiCMOS for IEEE 802.11 b/g.

Currently, the cellphone industry is moving towards an integrated CMOS solution for power amplifiers. Cheaper phones for consumers and better bottom lines for companies are the result of this. The goal of this thesis is to investigate the use of pulse width modulation in a high efficiency integrated CMOS power amplifier for a wireless application. Though high efficiency CMOS power amplifiers ex...

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulatedcascode differential gain enhancemen...

In this paper a high efficiency PWM CMOS audio power amplifier is proposed. The original idea is based on the difference close-loop feedback technique and the difference pre-amp. Thus, we conceive a rail to rail comparator with a constant gm. This rail-to-rail PWM comparator with hysteresis architecture has been embedded in the audio power amplifier. The simulation results based on the TSMC 0.1...

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential differen...

Ultrasonic receiver circuit with Phase-locked loop 4046 Ultrasonic amplifier with high amplification factor · Transformer-coupled ultrasonic transmitter circuit. General-Purpose CMOS Rail-to-Rail Amplifier. ADP7104. 20 V, 500 mA, Low The circuit shown in Figure 1 is a completely self-contained distance sensor that utilizes an ultrasonic transmitter and sensitive analog receiver in conjunction.

A 1.8 GHz low-noise amplifier has been designed and fabricated in a standard 0.35 pm CMOS process. Measurement results indicate that the amplifier has a forward gain (S21) of 10.5 dB and a noise figure of 3.94 dB, while consuming 40 mW from a 2.5 V supply.

The design of a fully differential CMOS transconductance operational amplifier is presented. Topology selection, compensation, biasing, and common mode feedback are discussed. Design analysis and simulations are presented demonstrating that the amplifier exceeds the specifications for application in the first stage of a 13-bit pipelined A/D converter, while dissipating an average of 66 mW of po...

This paper demonstrated the first 2-stage, 2.8W, 1.8V, 1.9GHz fully-integrated DAT power amplifier with 50Ω input and output matching using 0.18μm CMOS transistors. It has a small-signal gain of 27dB. The amplifier provides 2.8W of power into a 50Ω load with a PAE of 50%.