Mathematical analysis and empirical evaluation of the solid state equation PowerCMOS = P = C ⋅V2 ⋅ f ⋅ N ⋅%N is presented in this paper which identifies a measurable metric for evaluating relative advantages of ASIC, DSP, and RISC architectures for embedded applications. Relationships are examined which can help predict relative future architecture performance as new generations of CMOS solid s...

The design of a sensing channel for implantable cardiac pacemakers in CMOS on Silicon-on-Insulator (SOI) technology is presented. The total current consumption is lowered to only 110nA thanks to the optimization at the architectural level, the application of a new class AB design approach at the operational transconductance amplifier (OTA) and the exploitation of the improved characteristics of...

The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit, proposed over 15 years ago in [1], now appears to be a reality. One such optoelectronic-VLSI (OE-VLSI) technology is based on the hybrid flip-chip area-bonding of GaAs/AlGaAs Multiple-Quantum Well (MQW) electro-absorption modulator devices directly onto active silicon CMOS circ...

The objective of this paper is to design a Low-Voltage, Low-Power and High-Gain Operational Amplifier used for high speed compensated CMOS op-amp which specifies open loop circuit parameters to obtain enhanced gain, settling time and closed loop stability An Op-Amp is designed in a 0.18 μm standard digital CMOS Technology The low noise high speed Op-Amp is designed using 180nm CMOS technology a...

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance ass...

This paper reviews the development of CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors. MAPS are developed in a standard CMOS technology. In the imaging field, where the technology found its first applications, they are also known as CMOS Image Sensors. The use of MAPS as a detector for particle physics was first proposed at the end of 1999. Since then, their good perform...

iii Acknowledgements iv Abstract CMOS technology scaling in recent decades has enabled a phenomenal performance improvement in microprocessors by allowing designers to increase the level of integration at higher clock frequencies. Unfortunately, technology scaling has also created unprecedented design challenges, including, but not limited to, the devices' leakage current, the interconnect dela...

This paper presents an excitatory CMOS power consumption and circuit size, which is ideal for integrator is built using operational amplifier. This circuitry is realized in TSMC 0.18μm CMOS Technology. Switched Capacitor (SC) integrator circuit The SC integrator correlated double

In this paper, A CMOS comparator with high low power application is presented. The comparator has been designed and simulated in 180nm CMOS technology. It is designed to sense low voltage using Double-Tail Dual-Rail Dynamic switching method.