Sparse Distributed Memory is a content addressable, associative memory terhnique which relies on close memory items tending to be clustered together, with some abstraction and blurring of details. This paper discusses the limitations of the original model. Then, we propose a method which improve Sparse Distributed Memory efficiency through an adaptive threshold. The results obtained are good an...

Computational properties of use of biological organisms or to the construction of computers can emerge as collective properties of systems having a large number of simple equivalent components (or neurons). The physical meaning of content-addressable memory is described by an appropriate phase space flow of the state of a system. A model of such a system is given, based on aspects of neurobiolo...

-The mean field theory ( MFT) learning algorithm is" elaborated and explored with respect to a variety of tasks. MFT is benchmarked against the back-propagation learning algorithm ( BP) on two different.feature recognition problems: two-dimensional mirror symmetry and multidimensional statistical pattern classification. We find that while the two algorithms are very similar with respect to gene...

Index generation functions model content-addressable memory, and are useful in virus detectors and routers. Linear decompositions yield simpler circuits that realize index generation functions. This paper proposes a balanced decision tree based heuristic to efficiently design linear decompositions for index generation functions. The proposed heuristic finds a good linear decomposition of an ind...

JCHPS Special Issue 1: February 2017 www.jchps.com Page 197 Design of Low Power Content-Addressable Memory using Master–Slave Match Line P. Nithya & S. Tamilselvan Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Tamil Nadu. *Corresponding author: E-Mail: [email protected] ABSTRACT Content-Addressable Memory is an extension of ordinary m...

The emerging technology using Field Programmable Gate Arrays (FPGA’s) is the leading architectures with look-up tables (LUT’s) based design plays the major role in the chip design. The memory unit and controller are the basic units and it performs the operation based on the lookup table methods. The logic circuit is designed based on requirements. The Ternary content addressable memories (TCAMs...