We consider the fundamental delay bounds for scheduling packets in an N × N packet switch operating under the crossbar constraint. Algorithms that make scheduling decisions without considering queue backlog are shown to incur an average delay of at least O(N). We then prove that O(log(N)) delay is achievable with a simple frame based algorithm that uses queue backlog information. This is the be...

* This material is based upon work supported by the National Science Foundation under Grant No. 9875177. Abstract Input-buffered switches with virtual output queueing require crossbar switch matrix scheduling algorithms. Existing scheduling algorithms are non-deterministic and are based on parallel and iterative request-grant-accept arbitration schemes. This presents challenges to flow-level sc...

This paper describes the design of a novel CMOS 2 Gb/s asymmetric serial link. The serial link is designed for systems that use high speed chip-to-chip communications. In such designs, power dissipation is a common problem, particularly when multiple serial links are required on one chip. The power arises primarily from the phase adjustment circuitry used to align data with the clock. This circ...

High-performance computers have historically been one of the main drivers behind high-performance networks. A significant body of work into network toplogies, signalling techniques, routing, broadcast and reduction algorithms exists and continues to grow. However, to this day, modern high-performance computers, including the RIKEN“Next-Generation”supercomputer (NSC), are partitioned such that t...

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major br...

We propose a multicast-capable free-space optical switch using tri-state switching elements (SEs) and investigate its complexity and loss. We also show that an N-input M-output multicast-capable switch requires only N ·M non-movable tri-state SEs. OCIS codes: (060.1810) Buffers, couplers, routers, switches, and multiplexers; (060.4255) Networks, multicast.

Multistage network based input-buffered ATM switches, which have been studied extensively in the recent past, are cheaper compared to crossbar designs but suffer from elaborate cell selection methods or expensive network setup. In this paper, a fast cell selection method is proposed to avoid slow cell selection and costly network setup for these designs. In particular, we propose network hardwa...

As buffer-less scheduling algorithms reach their practical limitations due to higher port numbers and data rates, buffered crossbars have gained a lot of interest recently because of the great potential they have in solving the complexity and scalability issues faced by their buffer-less predecessors. In particular, the internally buffered switching architecture was shown, through distributed s...

Need for high speed internet connectivity has lead to a substantial research in switching systems. Buffered crossbar switches have received a lot of attention from both research and industrial communities due of its flexibility and scalability. Designing a scheduling algorithm for buffered crossbar switches without starvation is a major challenge as of now. In this paper, we proposed a Delay ba...