Abstract— This paper proposes a procedure for converting a class of Op Amp-, FTFN-, CCand CFAbased voltage mode circuits to corresponding current mode circuits without requiring any additional circuit elements and finally from Op Amp-based voltage mode circuits to any of the FTFN, CC and CFA current mode circuits. The latter circuits perform better at high frequency than the former ones. The va...

Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristi...

In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in spee...

The purpose of this study was to optimize the thickness of anodizing Aluminum coatings processed under pulse current mode through the Design of Experiments (DOE) method. Thickness measurement, polarization and electrochemical impedance spectroscopy were employed to take Thickness and corrosion behaviors of the anodized coatings into consideration. Also, Field-emission scanning electron microsco...

A digital integrated circuit to realize multi-chip phase synchronization of fractional-N PLL with local oscillator divider is designed. An offset fractional frequency ratio added in difference calculation, which effectively avoids the large calculation error under some special ratios. Different from traditional one-time synchronization, a method tracking mode proposed, can further reduce error....

In this paper design of an improved high speed efficient fuzzy logic controller in switched-cap technique is proposed. The controller takes advantage of an improved fuzzifier with less power consumption compared to what previously has been proposed, a high speed minimum circuit (MIN) and a new structure for high speed voltage mode divider. Pipeline structure, high speed, low power supply and vo...

The objective of this paper is to implement a two-phase, interleaved, bidirectional DC/DC converter topology with an improved voltage conversion ratio for electric vehicle (EV) and DC-microgrid systems. In this study, a two-phase interleaved charge-pump topology is introduced to achieve a high voltage conversion ratio with very simple control circuits. In discharge mode, the circuit topology ac...

An easier force single-stage clock multiband adaptable divider with joining together P&s counter is displayed. Changed manifestation of augmented accurate single-stage clock (E-TSPC) based gap by-2/3 counter was planned utilizing pass transistor rationale, which requires stand out transistor to execute both the numbering rationale and the mode determination control. This technique has been inve...