In very deep submicron technologies (< 0.13 μm) the leakage power consumption becomes an important contribution to total power consumption. Consequently a new low-power design methodology will be required at circuit, architectural and system levels. This paper focuses on architecture comparison and aims at selecting the one with the minimum total power consumption by simultaneously optimizing s...

Coupled switched capacitance causes crosstalk in ultra deep submicron/nanometer VLSI fabrication, which leads to power dissipation, delay faults, and logical malfunctions. We present the first memoryless transition bus-encoding technique for power minimization, errorcorrection, and elimination of crosstalk simultaneously. To accomplish this, we generalize balanced sampling plans avoiding adjace...

We use a combination of several different types of lithography to generate Bragg-grating devices. In interference lithography, two coherent laser beams are crossed, generating a standing-wave interference pattern. This standing-wave pattern is used to expose photoresist, yielding a coherent deep-submicron-period grating. This grating can be used directly as the device grating or it can serve as...

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement and power reduction. Based o...

In deep-submicron technologies the primary component of delay is shifting from logic gates to the interconnect network. Buses can no longer be considered as a set of independent lines that don’t interact. A more appropriate model would treat the bus as a distributed system, where a transition on a line would affect adjacent lines as well. However, the transitions on the buses can be grouped int...

Radiation effects account for increasing soft error occurrences in deep submicron circuits. A method for calculating an upper bound for the width of an erroneous pulse that may reach a flip flop or a primary output is presented. This is required in order to determine pulse removal (PR) circuit characteristics for error correction at each flip flop or primary output side. Key-Words: Soft errors,...

We investigate the impact of varying the grain boundary (GB) position on the output (Id–Vd) characteristics of submicron single GB polysilicon thin film transistors (TFTs), by two-dimensional (2D), drift-diffusion based, device simulation. We employ a localized GB trapping model with a distribution of both donor-like and acceptor-like trap states over the forbidden energy gap of the GB region. ...

Kurzreferat In der vorliegenden Arbeit wird der Mixed Gates (MG) Ansatz zur Reduzierung des Leckstromverbrauchs in aktuellen und zukünftigen Technologien vorgestellt. Der Ansatz stellt eine Erweiterung der verbreiteten Dual Threshold CMOS (DTCMOS) und Dual Tox (DTOCMOS) Techniken dar und basiert auf gemischten Gattern mit unterschiedlichen Transistortypen. Zusätzlich wird ein erweiterter Algori...

High-reliability performance of a Q-band MMIC amplifier fabricated using TRW’s 0.1 μm production AlGaAs/GaAs HEMT process technology is reported. Operating at an accelerated life test conditions of Vds=4.2V and Ids=150mA/mm, two-stage balanced amplifiers were lifetested at threetemperatures (Ta=255 C, Ta=270 C, and Ta=285 C) in air ambient. The activation energy (Ea) is as high as 1.7 eV, achie...

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flipflop based on a sense amplifier and a photon-emitting device. This method can be used even with deepsubmicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the ...