We have demonstrated high-performance deep-submicron inversion-mode InGaAs MOSFETs with gate lengths down to 150 nm with record Gm exceeding 1.1 mS/μm. Oxide thickness scaling is performed to improve the on-state/off-state performance and Gm is further improved to 1.3 mS/μm. HBr pre-cleaning, retro-grade structure and halo-implantation processes are first time introduced into III-V MOSFETs to s...

Over the past 50 years of the semiconductor industry, the size of MOSFETs has been scaled down obeying the Moore’s law: feature sizes of transistors are scaled at a rate of approximately 0.7 times every 18 months. However, as CMOS technology approaches nanoscale region, researchers face with critical technology barrier known as short channel effect. While the gate voltage fully controls the cha...

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited ch...

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction cha...

The Triple gate FinFET architecture has emerged as a viable contender for the ultimate scalability of CMOS devices. FinFET structure offers better control over device leakage currents than the conventional bulk MOSFET structure. In this paper, we present the 6 transistor (6T) SRAM cell implementation using the 22 nm gate length FinFET devices modeled using a 3-D device simulator. The performanc...

In the past 30 years, the semiconductor industry has been expanded drastically by the downsizing of the transistors. The progress of the downsizing, however, has increased the chip power. As the battery-powered products, like mobile computers and mobile phones, become popular, the low-power design becomes the one of the most important issues of the LSI design. On the other hand, high-performanc...

Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in stack. The device process parameters like impact, nano-fin geometry variation, and power analysis along DC, Analog/RF, line...