ion. Streamlining the code can sometimes produce a significant improve-ment in simulation performance. 12.3.2 HDL Extensions and C++ There is a growing acceptance of high-level languages (HLLs), particularly C andC++, for conceptual or system level modeling. One reason for this is the fact that amodel expressed in an HLL usually executes more rapidly than the same modelexpressed...

A new approach to parallel fault simulation for sequential circuits based on Binary Decision Diagrams (BDD) is proposed. The efficiency of BDDs for simulation is well known. However, traditional BDDs are not well-suited for fault simulation. Furthermore, up to now, they have not been used for parallel simulation. In the paper, a new class of BDDs is presented, called Structurally Synthesized BD...

In an environment such as underwater channel where placing test equipments are difficult to handle, it is much practical to have hardware simulators to examine suitably designed transceivers (transmitter/receiver). The simulators of this kind will then allow researchers to observe their intentions and carry out repetitive tests to find suitable digital coding/decoding algorithms. In this p...

Sigma-Delta Analog to Digital Converter with digital implementation techniques is simulated. The differential pin based and inverter based architectures are discussed. Simulation of the proposed architecture with Virtex-4 FPGA I/Os is performed and analysis carried out using HSPICE to estimate the typical achievable clock speeds. The results demonstrate 200MHz clock speeds on LVPECL differentia...