Thin yttria films were investigated for use as gate dielectrics in carbon nanotube field-effect transistors (CNTFETs) with the gate length scaled down to sub-50 nm size. The yttria film provided an omega-shaped gate dielectric with a low interface trap density, a low average sub-threshold swing of 74 mV per decade for both long and short CNTFETs, and a small drain-induced barrier lowering. It w...

Metal–oxide–semiconductor field-effect transistors ~MOSFETs! with a wire-channel and wrap-around-gate ~WW! structure were fabricated using electron beam lithography and reactive ion etching. The smallest devices have a 35 nm channel width, a 50 nm channel thickness, and a 70 nm channel length. Measurements showed that as the channel width of WW MOSFETs decreased from 75 to 35 nm short channel e...

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangul...

A triple metal double gate (TM-DG) MOSFET with high-k dielectrics has been proposed to overcome the short channel effects. We are using top and bottom metal gates with different work functions to screen the effect of drain (DIBL effect). It has been found that this is effective in reducing the short channel effects. The metal gates have been used to remove the poly silicon depletion of conventi...

This paper investigates the impact of quantum effects on the increase of short channel effects in III–V MOSFETs. First of all, contrary to the results obtained by other groups [1,2], quantum confinement has been found to play no role on the short channel effects occurring in the subthreshold regime. In this regime, the main origin of the increase of SCEs is simply due to the higher dielectric c...

The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnec...

Please cite this article in press as: Hwang E et a logic applications. Solid State Electron (2011), d In this paper, the scalability of In0.7Ga0.3As QWFET is investigated using two-dimensional numerical drift–diffusion simulation. Numerical drift–diffusion simulations were calibrated using experimental results on short-channel In0.7Ga0.3As QWFETs [7] to include the effects of velocity overshoot...

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthr...

In the light of a modified two-dimensional Poisson equation, an analytical model for the threshold voltage Vth of deep-submicrometre MOSFETs is developed, which can show Vth’s nonlinear dependence on drain voltage Vds . Meanwhile, by introducing a normalized effective gate voltage Vgtx to obtain continuous channel charge characteristics from the subthreshold to the strong inversion region and p...