Reliability and robustness have been always important parameters of integrated systems. However, with the emergence of nanotechnologies reliability concerns are arising with an alarming pace. The consequence is an increasing demand of techniques that improve yield as well as lifetime reliability of today’s complex integrated systems. It is requested though, that the solutions result in only min...

In any VLSI circuit, power consumption is very important factor that should be taken into consideration. Generally, dynamic power consumption is more dominant when compared to that of static. To reduce the internal switching activity rate of the circuit under test (CUT), we can recombine testing vector to raise the correlation between testing vector. Random Single Input Change (RSIC) test theor...

Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on mem...

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. It has been proven that Single Input Change (SIC) test s...

A modi ed type system for the Ruby VLSI design language is described, which adds directional information to the types of Ruby relations. Reasons for wishing to do so are discussed, and a realisation of the re ned typing scheme is outlined. In order to deal with one otherwise troublesome case, constraints are added to the type system to maintain principal types in the presence of direction infor...

Testing of present day VLSI circuits with standard linear scan procedures using the Built-In Self Test (BIST) takes a significant amount of time, with the sheer number of sequential elements running into tens of thousands. Using the Illinois Scan Architecture, we propose to significantly reduce the test application time, by dividing the scan chain into multiple partitions and shifting in the sa...

The Multiple On-chip Signature Checking architecture proposed in [l] is an effective BIST architecture for testing the finctional units in modern VLSI circuits. It is characterized by low aliasing, low area overhead and low test ing time. However, a straight forward application of this architecture in testing the embedded RAMs will result in excessive area overheads. In this paper we propose a ...

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to gro...

Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method ...

There exists a lack of balance between design and testing topics in microelectronic curricula. However, boundary scan as a virtual probe presents an opportunity to teach testing and design for testability in such a curriculum. This effort is facilitated by the use of IEEE standards, universal acceptance in industry, and the availability of low cost test equipment. This paper introduces a librar...