This paper addresses the problem of Test Effectiveness (TE) evaluation of a FPGA BIST solution, through Hardware Fault Simulation (HFS). A novel HFS technique is proposed, that efficiently, using partial reconfiguration, ascertain (or not) the BIST. The proposed methodology can be particularly useful for signature fault dictionary building and for applications in which multiple fault injection ...

Changes in the physicochemical conditions of process unit, even under control, may lead to what are generically referred to as faults. The cognition of causes is very important, because the system can be diagnosed and fault tolerated. In this article, we discuss and propose an artificial neural network that can detect the incipient and gradual faults either individually or mutually. The mai...

Transformer fault diagnosis and repair is a complex task that includes many possible types of faults and demands special trained personnel. In this paper, Petri Nets are used for the simulation of transformer fault diagnosis process and the definition of the actions followed to repair the transformer. An integrated safety detector relay is used for transformer fault detection. Simulation result...

Abstract: This paper describes analysis, modeling and simulation of electrical transient fault-current detection in power systems. The proposed modeling is based on simple numerical integration only, which is able to efficiently handle some sophisticated calculation. The proposed fault detector methods are sliding root mean square (SRMS) and PQR transformation technique. In this paper, an abnor...

In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors test set partition and fault set partition. The sequential algorithm for fault si...

For sequential circuit path delay testing, we propose a new update rule for state variables whereby flip-flops are updated with their correct values provided they are destinations of at least one robustly activated path delay fault. Existing algorithms in the literature, for robust fault simulation and test generation, assign unknown values to off-path latches that have non-steady signals at th...

We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signiicantly reducing the number of injected faults and faulty-event evaluations. Speciically, we dynamically reduce injection of two types of faults: (1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a ip-op or primary ou...

The recently established computational equivalence between the traditional message-passing model and the mobile-agents model is based on the existence of a mobile-agents algorithm that simulates the execution of message-passing algorithms. Like most existing protocols for mobile agents, this simulation protocol works correctly only if the agents are fault-free. We consider the problem of perfor...